1. Field of the Invention
The present invention relates to a variable length coder (VLC) for use in a device which codes an image signal with high efficiency.
2. Description of the Prior Art
One conventional variable length coder will be described below with reference to FIGS. 1 and 2 of the accompanying drawings.
FIG. 1 shows, in block form, a conventional variable length coder for coding data, such as image data, having a maximum code length of 16 bits in the illustrated example.
FIG. 2 illustrates internal data status or output data of various circuit components of the variable-length coder shown in FIG. 1.
In FIG. 1, 16-bit data supplied to an input terminal INPUT is converted by a coding table 32 into a variable length code VLC which is transferred to a barrel shifter (SFT) 33. The variable length code VLC outputted from the coding table 32 has a bit length shorter than the bit length of the 16-bit data. In FIG. 2, vertically elongate rectangular frames represent data whose vertical lengths are indicative of bit numbers. For example, the variable length code VLC outputted from the coding table 32 is 16 bits, and the internal data of the barrel shifter 33 is 32 bits.
As shown in FIG. 1, the coding table 32 also outputs a code length VL of the variable length code VLC.
A shift controller (R.phi.) 34 accumulates code lengths VL, and outputs the accumulated code lengths VL as a shift SF, which is representative of the number of bits of the data supplied to the input terminal INPUT. The shift SF can have a value of 16 at maximum. If the shift SF exceeds 16, then it is equalized to the difference between its value and 16. In the event that the shift SF is in excess of the maximum value, the shift controller 34 outputs a flag FL of "1" indicating an overflow. If the shift SF has no overflow, the shift controller 34 outputs a flag FL of "0".
The variable length code VLC transferred to the barrel shifter 33 is placed in a register in the barrel shifter 33 by the shift SF outputted from the shift controller 34, which shift SF represents the code length VL of the variable length code VLC of the preceding sample.
The data stored in the register in the barrel shifter 33 is then divided into high- and low-order 16 bits. The low-order 16 bits, denoted at BS1, are transferred through an OR gate 35 to a register (R1) 36. The high-order 16 bits, denoted at BS2, are transferred directly to a register (R2) 37. Each of the registers 36, 37 comprises a flip-flops, and holds the data transferred at a present time and outputs the held data at a next time.
The output data from the registers 36, 37 are supplied to a multiplexer (MUX) 38. The multiplexer 38 selects the output data from either the register 36 or the register 37. Specifically, when the flag FL outputted by the shift controller 34 is "1", the multiplexer 38 selects the output data from the register 36, and when the flag FL outputted by the shift controller 34 is "0", the multiplexer 38 selects the output data from the register 37.
At a time n=0, the variable length code VLC outputted from the coding table 32 is composed of data A which is valid variable length code data of 5 bits and data 0 which is invalid data.
At the time n=0, since the variable length VL of the preceding sample is 0, the internal data of the barrel shifter 33 contains the data A of the variable length code VLC starting from the LSB thereof, as shown in FIG. 2.
At the time n=0, the registers 36, 37 have internal data status R1, R2 of 0, i.e., the data stored in the registers 36, 37 are nil, as shown in FIG. 2.
At a next time n=1, it is assumed that the variable length code VLC has valid variable length code data B whose code length VL is 2 bits. At this time, the shift SF is of 5 bits which is the code length VL the data A of the variable length code VLC at the preceding time n=0. Therefore, the data in the barrel shifter 33 is shifted 5 bits such that the data B is stored in a position which corresponds to a 6th bit counted from the LSB of the data in the barrel shifter 33. The register 36 outputs the data at the preceding time n=0, and the register 37 outputs 0.
At a time n=2, it is assumed that the variable length code VLC has valid variable length code data C whose code length VL is 12 bits. At this time, the shift SF is 7 bits which are the sum of 5 and 2 bits that are the code lengths VL of the data A, B of the variable length codes VLC. The data in the barrel shifter 33 is shifted 7 bits such that the data C is stored in a position which corresponds to an 8th bit counted from the LSB of the data in the barrel shifter 33. The register 36 outputs data which is produced when the data BS1 outputted from the barrel shifter 33 and data MXO outputted from the multiplexer 38 at the preceding time are ORed. The data outputted from the register 36 is therefore the sum of the data A, B as shown in FIG. 2. The register 37 outputs 0.
At a time n=3, it is assumed that the variable length code VLC has valid variable length code data D whose code length VL is 10 bits. At this time, the shift SF is 19 bits which is the sum of the code lengths VL so far. Since the shift SF has a maximum value of 16 bits, the shift SF becomes 19-16=3 bits. Now, the shift controller 34 detects an overflow, and the flag FL is set to "1". The data outputted from the register 36 is produced by ORing the data outputted from the barrel shifter 33 so far. Inasmuch as the data C of the variable length code VLC exceeds the 16-bit range of the register 36 by 3 bits, the excess 3 bits are outputted from the register 37. At the same time, when the flag FL is set to "1", the data stored in the register 36 is stored in a buffer memory (BM) 39.
At a time n=4, the barrel shifter 33 shifts the data as shown in FIG. 2. Because the flag FL has been set to "1" at the preceding time, the data outputted from the register 36 is produced by ORing the data outputted from the register 37 at the preceding time and the data D of the variable length code VLC at the preceding time.
The aforesaid operation is subsequently repeated as shown in FIG. 2.
Heretofore, once the maximum code length of the variable length code VLC is determined, the data range of the barrel shifter 33 and the data range for the buffer memory 39 are determined. Consequently, the conventional variable length coder cannot be constructed with system flexibility.
The article "Digital Coding of Component Television Signals for Contribution--Quality Applications in the Range 34-45 Mbits " CMTT--2/6--E 8 March 1991 shows use of a variable length code having a maximum code length of 18 bits, and bit stuffing in units of 16 bits with 16-phase-interleave error correction. In such an application, it is desirable to code and output data in the range of 16 bits though the maximum code length is of 18 bits. However, the conventional variable length coder fails to provide such flexibility.
FIGS. 3 and 4 of the accompanying drawings show a conventional higher-speed variable length coder which is composed of two parallel variable length coders each of the structure shown in FIG. 1.
In FIG. 3, each time a predetermined number of data to be coded are supplied, they are alternately stored in FIFO memories 41, 42, and the stored data are read therefrom at a rate which is half the rate at which they have been stored. The data thus read from the FIFO memories 41, 42 are then coded by respective variable length coders 43, 44. The coded data outputted from the respective variable length coders 43, 44 are then stored in FIFO memories 45, 46, respectively, from which the stored data are alternately read as output signals at a rate twice the rate at which they have been stored.
However, since the variable length coders 43, 44 operate independently of each other, no matching can be achieved between the data outputted from each of the variable length coders 43, 44. Therefore, the coded data may contain invalid data in a region where they are joined to each other, as shown hatched in FIG. 4. When such invalid data are included, they tend to lower the efficiency with which the coded data are transmitted.